A Through-Silicon-Via (TSV) enabled 3D integration technology can provide a high packaging density which enables more microelectronic devices to be contained per unit volume, a shorter signal path to reduce parasitic capacitances, an increased operation frequency for the chips, etc. and thus attracts many attentions from academic and industrial circles. However, the three-dimensionally stacked chips with TSV interconnection still face challenges from several aspects such as TSV fabrication, TSV insulation, TSV filling with copper electroplating, temporary bonding of ultra-thin wafers, etc., of which those from aspects such as micro-solder balls or bonding pad fabricating as well as low temperature bonding thereof, thermal managing for stacked chips, and signal managing between vertically adjacent chips inside the stacks are particularly notable. The electrical interconnection and physical connection between the vertically adjacent chips in the stacks require a bonding that is based on micro-solder balls or bonding pads for carrying out. On one hand, the TSV enabled 3D integration technology requires downscaling of micro-solder balls or bonding pads to maintain its technological advantages, with a typical size of the micro-solder balls or bonding pads scaling down from hundreds micrometers to tens micrometers even to several micrometers. On the other hand, the TSV enabled 3D integration technology depends on micro-solder balls or bonding pads to achieve a reliable electrical interconnection and a physical connection, while scaling down of the micro-ball or bonding pads is less favorable for reliable electrical and physical connection. In addition, the increase in the number of stacked layers requires at least one or more times of bonding and reflow processes to implement the bonding between vertically adjacent chips of the stacks. In this case, the micro-solder balls or bonding pads having completed one time of bonding need to go through another bonding and another reflow processes to implement a multi-layered stack, which would cause damages to the micro-solder balls or bonding pads having already been bonded, and influence the reliability.
Moreover, the power dissipation per unit volume has a rise with an increase of the number of the stacked layers. When the heat released from the chips inside the stacks increases, it is liable to generate hotspots inside the stacks, which results in a performance degradation of the stacked chips. This brings severe threat to the reliability of the stacks.
The TSV enabled 3D integration technology desires thickness of each layer of the chips in the stack keep declining, which shortens a signal path between vertically adjacent chips inside the stacks, and enhances the performance of the stacked chips as well as the package density. However, when the thickness of the chips located in the stacks decreases, the signals transmission across the surfaces of the vertically adjacent chips in the stacks may be interfered with each other, which is not favorable for the chip stacks to function normally.